ESR or Equivalent Series Resistance, is a term that lumps all dissipative losses in the capacitor into one number. The total energy loss in a capacitor is a function of dielectric losses attributed to polarizing mechanisms of the electric field on the molecular structure of the dielectric, and ohmic loss from electrodes and termination metals.

The ESL or Equivalent Series Inductance of the lumped element model of the capacitor (series RLC capacitor model) accounts for the resonance mechanism. The model is considered valid up to approximately 1.5 times the first series resonance frequency. Performance beyond the first series resonance is evaluated using distributed transmission lines.

Resonances may continue to appear in the capacitor response beyond the first parallel resonance. The appearance of the resonances at all and the Q and frequency of the resonances can be modified by manufacturing and material tolerances and the prevailing loss mechanisms in the system to include the structure in which the capacitor is mounted. Part/mounting specific modeling and s parameter measurements are advised if detailed performance information is required.

The interaction between the structure of the capacitor and the substrate and ground plane affect the equivalent impedance and subsequent resonant behavior of the capacitor. Critical applications may dictate device/board specific modeling and measurement to insure satisfactory results

Q is a fundamental expression of energy losses in a dissipative, resonant system and may be expressed as Q = 2p (energy stored in a system)/(energy lost in the system). Following classical mathematical development, Q can be expressed as the ratio of the capacitive reactance to the ESR at the frequency of interest or Q = Xc/ESR. Q can be accurately measured and it provides a repeatable technique for quantifying low loss, “High Q” passive components.

Loss tangent, a synonym for dissipation factor, is a quantification of loss in the capacitor. The loss tangent is the tangent of the phase angle relationship between capacitor voltage and capacitor current as the angle departs from the theoretical 90 degree value as a result of loss mechanisms within the capacitor. d is also known as the loss angle.

tan d = DF = 1/Q = ESR/ Xc

Dissipation factor, a synonym for loss tangent, is a quantification of the loss in the capacitor. Mathematically it is equal to the reciprocal of Q and, generally, is expressed as a %. DF = 1/Q = (ESR/ Xc) x 100 For a loss angle of 2 degrees, tan d = 0.035, and expressed as a percent DF = 3.5%. Thus 3.5 % of the power in the capacitor will be lost as heat.

Yes. Resulting from the difference in plate count necessary to achieve a given capacitance with different dielectric formulations [different dielectric constants], one may see differences in inductance. [Lower dielectric constant, i.e. AH material, more plates per cap value. Thus, lower ESR and ESL.]

The maximum applied voltage to include dc, peak AC, or a combination of both, should not exceed the rated working voltage of the capacitor.

Capacitance and dissipation factor for devices greater than 1000pF are tested at 1 KHz; devices of lower value are tested at 1 MHz. The testing of capacitors conforms to the guidance of military and industry standards.

Ceramic chip capacitors are constructed from materials that are grouped into two classes based on electrical performance and basic chemical composition. Class I dielectrics generally include lower values of dielectric typically under 150. Class I dielectrics demonstrate a linear relationship between the applied electric field and the dielectric polarization, are stable with temperature, display a linear capacitance variation with temperature, present lower dielectric loss, experience no dielectric absorption, and experience no aging. Class II dielectrics offer significantly higher dielectric constant and facilitate higher capacitance values in a given package size but demonstrate significantly poorer temperature, voltage, aging, and loss performance.Ceramic chip capacitors are constructed from materials that are grouped into two classes based on electrical performance and basic chemical composition. Class I dielectrics generally include lower values of dielectric typically under 150. Class I dielectrics demonstrate a linear relationship between the applied electric field and the dielectric polarization, are stable with temperature, display a linear capacitance variation with temperature, present lower dielectric loss, experience no dielectric absorption, and experience no aging. Class II dielectrics offer significantly higher dielectric constant and facilitate higher capacitance values in a given package size but demonstrate significantly poorer temperature, voltage, aging, and loss performance.

Some of the higher dielectric ceramic formulations, ferroelectric ceramics, display a crystalline change that causes a decrease in capacitance with time. This is a consequence of the basic chemical formulation, the microstructure of the ceramic, and the relaxation of the strain energy within the crystalline lattice. The reference time, t = 0, for the aging phenomenon is the time which the ceramic was last exposed to the Curie temperature. Curie temperatures vary with ceramic formulations and can range from room temperature to 150 oC. Thermal influences due to the external environment and manufacturing processes can reset the aging clock. This variation in capacitance is predictable and repeatable. It should be considered during the design phase to insure selected capacitance values will be adequate for the anticipated life of the application. Operating temperatures should not exceed the maximum specified component temperatures.

Piezoelectricity is the phenomenon resulting from the coupling of mechanical and electrical systems. In crystalline materials displaying piezoelectricity the stress [mechanical system] is coupled to the electromagnetic system through the dielectric polarization vector. Resultantly, a component capable of coupling mechanical stimulus [vibration] into an electrical system can introduce spurious electrical signals into the system.

Components utilizing non-linear dielectrics or containing magnetic materials can support the generation of spurious signals.

Dielectric absorption refers to the ability of some dielectrics to retain charge after the capacitor has been discharged. The phenomenon is attributed to time dependent polarization relaxation and is predominantly a factor in the high dielectric constant materials.

The current carrying capacity of a capacitor is limited by voltage breakdown and/or thermal dissipation. Breakdown attributed to excessive voltage, Ipeak times Xc , can create dielectric failure. The rated working voltage number should not be exceeded. Under certain conditions the voltage developed across the capacitor can exceed the breakdown voltage of the surrounding environment [air] and a corona can be established along the surface of the capacitor resulting in destruction of the capacitor. Thermal heating due to excessive power dissipation within the capacitor [Power dissipated = Irms 2 x ESR] and the inability to conduct the heat away can lead to failure. Applications can be different [substrate materials, mounting, ambient temperature, etc.], resultantly, it is very difficult to predict actual thermal performance of a specific capacitor in given application. It may be necessary to perform measurements of temperature rise under actual application conditions and establish the thermal resistance for the specific mounting configuration. The maximum specified operating temperature of the capacitor should not be exceeded.

Applications requiring the best stability should employ capacitors based on the AH, the CF, or the UL ceramic formulations. These display temperature variations of less than P90 +/- 30 ppm, less than 0 +/- 15 ppm, or less than 0 +/- 30 ppm respectively. For RF bypassing applications the effects of via and ground pad geometry can shift the frequency of maximum isolation. The effects of via inductance of capacitor performance can be modeled through the use of CapCAD. DC blocking applications typically require a broad range of low loss, resonant free, frequency coverage. The upper limit of bandwidth over which insertion loss meets specification is determined by the location of parallel resonances. CapCAD can provide design guidance as to the location of parallel resonances for the capacitor of interest. For maximum resonant free bandwidth custom broad band blocks such as the C06BLBB2X5UX, the C08BLBB1X5UX, the MILLI-CAP family of components, or the OPTI-CAP are recommended. High power applications require the use of the larger chip capacitors such as those from the C22 and C40 family. Select the lowest ESR capacitor with the appropriate working voltage rating. Insure proper mounting to the circuit to maximize heat transfer.

The substrate material and thickness, land pattern dimensions, proximity of adjacent conductors and components, mounting and attachment method – wire bonds, ribbons, or direct solder attach – can have a significant effect on reliability, ease of manufacture, thermal dissipation, and overall electrical performance. All need to be considered during the design phase.